This guide provides an overview of the key components, architecture, and documentation structure found within the V93000 test system technical documentation. 1. Introduction to the Verigy 93K (V93000) Platform
The test head must be mechanically aligned and locked to a wafer prober or packaged-device handler using precision docking systems. Incorrect alignment damages the interface pins.
Contains system power supplies, water cooling heat exchangers, and the primary system controller.
Defines the mapping between the physical tester channels and the logical names of the pins on the DUT. Levels and Timings: Levels: Dictate the exact voltages for logic high ( ) and logic low (
The fundamental manual describing the Graphical User Interface (GUI), configuration tools, and workspace management.
: Create the .pin layout to link your silicon pad names to the tester channels. Set up multi-site configurations (e.g., 4-site, 8-site, or 16-site testing) to optimize throughput.
A Full Cal is conducted periodically (e.g., monthly) or after hardware changes. Focused Cal targets explicit configurations (like a specific voltage array) right before a production run. Diagnostics and Verification
The SmarTest documentation details the software environment, which includes:
This physical channel is later mapped to a logical name (DUT pin name) within the SmarTest software workspace. 2. The SmarTest Software Workspace
A standard SmarTest test program relies on plain-text configuration files:
To verify the Verigy V93000 (now Advantest V93K) tester manual or documentation, you must access the official myAdvantest portal
: Engineers must periodically run system diagnostics without a performance board attached. The tool checks internal relays, measures reference voltages against built-in standards, and reports failing modules down to the specific relay or channel block.
Per-pin Parametric Measurement Units (PPMUs) for precise voltage/current metrics. Active loads for DC characterization. Power Infrastructure
The Verigy 93K tester is a modular, rack-mounted instrument consisting of the following main components:
Design test programs with true parallelism. Minimize shared resources within test methods to let multiple sites run concurrently without serial overhead.
: Outlines steps to run system-level self-tests to identify failing instrumentation cards.
By mastering the Verigy 93k manual, engineers can reduce test time, improve yield, and ensure that only the highest quality silicon reaches the market. Whether you are performing wafer sort or final package test, a deep understanding of SmarTest and the 93k hardware is your most valuable asset.
This guide provides an overview of the key components, architecture, and documentation structure found within the V93000 test system technical documentation. 1. Introduction to the Verigy 93K (V93000) Platform
The test head must be mechanically aligned and locked to a wafer prober or packaged-device handler using precision docking systems. Incorrect alignment damages the interface pins.
Contains system power supplies, water cooling heat exchangers, and the primary system controller.
Defines the mapping between the physical tester channels and the logical names of the pins on the DUT. Levels and Timings: Levels: Dictate the exact voltages for logic high ( ) and logic low (
The fundamental manual describing the Graphical User Interface (GUI), configuration tools, and workspace management. verigy 93k tester manual
: Create the .pin layout to link your silicon pad names to the tester channels. Set up multi-site configurations (e.g., 4-site, 8-site, or 16-site testing) to optimize throughput.
A Full Cal is conducted periodically (e.g., monthly) or after hardware changes. Focused Cal targets explicit configurations (like a specific voltage array) right before a production run. Diagnostics and Verification
The SmarTest documentation details the software environment, which includes:
This physical channel is later mapped to a logical name (DUT pin name) within the SmarTest software workspace. 2. The SmarTest Software Workspace This guide provides an overview of the key
A standard SmarTest test program relies on plain-text configuration files:
To verify the Verigy V93000 (now Advantest V93K) tester manual or documentation, you must access the official myAdvantest portal
: Engineers must periodically run system diagnostics without a performance board attached. The tool checks internal relays, measures reference voltages against built-in standards, and reports failing modules down to the specific relay or channel block.
Per-pin Parametric Measurement Units (PPMUs) for precise voltage/current metrics. Active loads for DC characterization. Power Infrastructure Incorrect alignment damages the interface pins
The Verigy 93K tester is a modular, rack-mounted instrument consisting of the following main components:
Design test programs with true parallelism. Minimize shared resources within test methods to let multiple sites run concurrently without serial overhead.
: Outlines steps to run system-level self-tests to identify failing instrumentation cards.
By mastering the Verigy 93k manual, engineers can reduce test time, improve yield, and ensure that only the highest quality silicon reaches the market. Whether you are performing wafer sort or final package test, a deep understanding of SmarTest and the 93k hardware is your most valuable asset.